Chalcogenide materials are an emerging class of commercial electronic materials that exhibit switching, memory, logic, and processing functionality. The basic principles of chalcogenide materials were developed by S. R. Ovshinsky in the 1960's and much effort by him and others around the world since then have led to advancements of the underlying science and an expansion of the field of application of chalcogenide materials.
Early work in chalcogenide devices demonstrated electrical switching behavior in which switching from a resistive state to a conductive state was induced upon application of a voltage at or above the threshold voltage of the active chalcogenide material. This effect is the basis of the Ovonic Threshold Switch (OTS) and remains an important practical feature of chalcogenide materials. The OTS provides highly reproducible switching at ultrafast switching speeds for over 1013 cycles. Basic principles and operational features of the OTS are presented, for example, in U.S. Pat. Nos. 3,271,591; 5,543,737; 5,694,146; and 5,757,446; the disclosures of which are hereby incorporated by reference, as well as in several journal articles including “Reversible Electrical Switching Phenomena in Disordered Structures”, Physical Review Letters, vol. 21, p. 1450-1453 (1969) by S. R. Ovshinsky; “Amorphous Semiconductors for Switching, Memory, and Imaging Applications”, IEEE Transactions on Electron Devices, vol. ED-20, p. 91-105 (1973) by S. R. Ovshinsky and H. Fritzsche; the disclosures of which are hereby incorporated by reference.
Another important application of chalcogenide materials is in electrical and optical memory devices. One type of chalcogenide memory device utilizes the wide range of resistance values available for the material as the basis of memory operation. Each resistance value corresponds to a distinct structural state of the chalcogenide material and one or more of the states can be selected and used to define operational memory states. Chalcogenide materials exhibit a crystalline state or phase as well as an amorphous state or phase. Different structural states of a chalcogenide material differ with respect to the relative proportions of crystalline and amorphous phase in a given volume or region of chalcogenide material. The range of resistance values is generally bounded by a set state and a reset state of the chalcogenide material. The set state is a low resistance structural state whose electrical properties are primarily controlled by the crystalline portion of the chalcogenide material and the reset state is a high resistance structural state whose electrical properties are primarily controlled by the amorphous portion of the chalcogenide material.
Each memory state of a chalcogenide memory material corresponds to a distinct resistance value and each memory resistance value signifies unique informational content. Operationally, the chalcogenide material can be programmed into a particular memory state by providing an electric current pulse of appropriate amplitude and duration to transform the chalcogenide material into the structural state having the desired resistance. By controlling the amount of energy provided to a chalcogenide material, it is possible to control the relative proportions of crystalline and amorphous phase regions within a volume of the material and to thereby control the structural (and memory) state of the chalcogenide material to store information.
Each memory state can be programmed by providing the current pulse characteristic of the state and each state can be identified or read in a non-destructive fashion by measuring the resistance. Programming among the different states is fully reversible and the memory devices can be written and read over a virtually unlimited number of cycles to provide robust and reliable operation. The variable resistance memory functionality of chalcogenide materials is currently being exploited in the OUM (Ovonic Universal (or Unified) Memory) devices that are beginning to appear on the market. Basic principles and operation of OUM type devices are presented, for example, in U.S. Pat. Nos. 6,859,390; 6,774,387; 6,687,153; and 6,314,014; the disclosures of which are incorporated by reference herein as well as in several journal articles including “Low Field Amorphous State Resistance and Threshold Voltage Drift in Chalcogenide Materials”, published in IEEE Transactions on Electron Devices, vol. 51, p. 714-719 (2004) by Pirovana et al.; and “Morphing Memory” published in IEEE Spectrum, vol. 167, p. 363-364 (2005) by Weiss.
The behavior (including switching, memory, and accumulation) and chemical compositions of chalcogenide materials have been described, for example, in the following U.S. Pat. Nos. 6,671,710; 6,714,954; 6,087,674; 5,166,758; 5,296,716; 5,536,947; 5,596,522; 5,825,046; 5,687,112; 5,912,839; and 3,530,441, the disclosures of which are hereby incorporated by reference. These references present proposed mechanisms that govern the behavior of the chalcogenide materials. The references also describe the structural transformations from the crystalline state to the amorphous state (and vice versa) via a series of partially crystalline states in which the relative proportions of crystalline and amorphous regions vary during the operation of electrical and optical chalcogenide materials.
Current commercial development of the chalcogenide materials and devices is also oriented toward the fabrication of arrays of devices. Chalcogenide materials offer the promise of high density memory, logic and neural arrays that can operate according to traditional binary data storage or according to a multilevel scheme. Chalcogenide arrays further offer the prospect of integrating, on a single chip, both memory and data processing capabilities, thereby enabling high speed operation.
In order to further expand the commercial prospects of chalcogenide phase change memories and switches, it is necessary to consider improvements in the chemical and physical properties of chalcogenide materials as well as refinements in the manufacturing processes. In most currently envisioned near-term memory applications, chalcogenide materials are operated in a binary mode where the memory states correspond to, or approximately correspond to, the set state and the reset state since these states provide the greatest contrast in resistance and thus facilitate discrimination of the state of the material during read out. An outstanding problem that has been identified in the prior art concerns the variability of the set and/or reset resistance of chalcogenide memory devices in the first several cycles of operation of the as-fabricated device. In the typical fabrication process for chalcogenide memory devices, the chalcogenide material is deposited on a lower electrical contact in a kinetically-inhibited or otherwise structurally disordered state and an upper electrical contact is subsequently deposited on the chalcogenide material. The resistance of the device following fabrication, and before the application of an electrical current pulse, may be referred to as the virgin resistance (RVirgin) of the device. Subsequent application of an electrical current pulse causes the material to achieve an initial set state having an initial set state resistance (RSet,0). The initial set state can reset to a first reset state by applying a higher amplitude electrical current pulse. The first reset state can be set by applying a set current pulse to produce another set state having a set state resistance RSet,1 and the process can be repeated over multiple set-reset cycles. For each set state achieved upon cycling, a resistance RSet,n can be measured where RSet,n corresponds to the resistance of the set state that is obtained after the device has been reset n times.
When the values of RVirgin and RSet,n are compared for different cycles (represented by different values of n), significant differences are commonly observed in the values of the virgin resistance and set resistance over the first several cycles. The most significant change normally occurs between RVirgin and RSet,0, with the deviations decreasing from RSet,0 to RSet,1 to RSet,2 etc. until the value of the set resistance stabilizes. A similar variability may also occur for the resistance of the reset state. For practical memory applications, variability in either the set resistance or reset resistance is undesirable because those resistances are commonly used as indicators for the memory states. Variability in the set resistance or reset resistance frustrates the objective of reliably and reproducibly establishing and detecting the memory states.
In order to eliminate the problem of variability in the prior art devices, it is necessary to undergo a formation process prior to utilization of chalcogenide memory devices in practical applications. The formation process involves post-fabrication electrical conditioning of the device and entails subjecting the device to a sufficient number of set-reset cycles to stabilize the resistances of the set state and/or reset state of the device so that the device is ready for its intended end use. An analogous need for formation or conditioning arises in the chalcogenide switching materials, where variability in the threshold voltage is commonly observed over the course of the first several switching events until a stable threshold voltage is attained. Because of the time and expense associated with the formation process, it is desirable to either simplify it (e.g. by reducing the number of cycling events required to achieve stable device performance) or eliminate it altogether.
In general terms, there are two general factors that potentially contribute to the variability in the resistances and threshold voltages of chalcogenide memory and switching devices. First, the chemical composition and/or physical characteristics of the chalcogenide material may influence the structural state of the chalcogenide upon deposition and the extent to which it varies upon cycling through the set and reset states. Stable set resistances, reset resistances and threshold voltages may require stable and consistent structural configurations of the chalcogenide over multiple cycles of setting, resetting and/or switching. The extent to which the structure varies over multiple cycles may depend on the composition of the chalcogenide. The composition may influence the crystal structure of the crystalline phase that forms upon setting, the relative proportions of crystalline and amorphous phase regions present at a particular resistance value, the spatial arrangement of crystalline and amorphous phase regions, and the kinetic and thermodynamic energy barriers associated with structural rearrangements and changes in phase. Some or all of these factors may contribute to the consistency of the set resistance, reset resistance and/or threshold voltage of a chalcogenide device. Amelioration of the variability of the set and reset resistances of chalcogenide devices through modifications of the chemical composition has been described in the co-pending parent application Ser. Nos. 11/200,466 ('466 application, filed Aug. 9, 2005) and 11/301,211 ('211 application, filed Dec. 12, 2005), the disclosures of which are incorporated by reference herein. More specifically, the '466 and '211 applications disclose a family of chalcogenide materials comprising Ge, Sb, and Te that contain a relatively low concentration of Ge and/or Te relative to standard prior art chalcogenide alloys such as Ge2Sb2Te5. The new materials were shown to reduce variability in the set resistance upon initial cycling from the virgin state and to require fewer cycles to complete formation.
A second factor that may contribute to variability in the resistances and/or threshold voltages of chalcogenide materials is the quality of the interface between the chalcogenide material and either or both of the upper and lower electrical contacts in a chalcogenide device. Since the measured resistance of a chalcogenide device includes the resistance of the interfacial region of the contacts, variability in the characteristics of the interface may lead to variability in the resistance values. Since this is an area that has not been adequately addressed in the prior art, there is a need to understand the factors that determine the quality of the interface and their effect on the reproducibility and consistency of the set resistance, reset resistance and/or threshold voltage of chalcogenide devices, especially upon initial cycling of an as-processed device.